CONFERENCES

N. Maillet, D. Lavenier, P. Peterlongo, Comparison of large scale metagenomic data in Tara Oceans project, Conférences Jacques-Monod, Integrative ecological genomics, Roscoff, France, 2011 [pdf] [link]

JF. Berthelot, C. Deltel, M. Giraud, S. Janot,L. Jourdan, D. Lavenier, H. Touzet, JF. Viarré, biomanycores.org: a repository of interoperable open-source code for many-core bioinformatics, Journées Ouvertes en Biologie, Informatique et Mathématiques (JOBIM), Paris, France, 2011 [pdf] [link]

M. Giraud, S. Janot, JF. Berthelot, C. Deltel, L. Jourdan, D. Lavenier, H. Touzet, JF. Viarré, Biomanycores, open-source parallel code for many-core bioinformatics, 12th Annual Bioinformatics Open Source Conference (BOSC 2011), Vienna, Austria, 2011 [pdf] [link]

J. Piat, F. Moreews, O. Collin, A. Cornu, D. Lavenier, SLICEE: A Service oriented middleware for intensive scientific computation, 7th IEEE 2011 World Congress on Services (SERVICES 2011), Washington DC, USA, 2011 [pdf] [link]

G. Chapuis, O. Filangi, P. Leroy, JM. Elsen, D. Lavenier, GPU Accelerted QTLMap, 15Th QTL-MAS Workshop, Rennes, France, 2011 [pdf] [link]

A. Cornu, S. Derrien, D. Lavenier, HLS Tools for FPGA : faster development with better performances, The 7th International Symposium on Applied Reconfigurable Computing, Queen's University of Belfast, 2011 [pdf] [link]

M. Darouich1, S. Guyetant, D. Lavenier, A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems, The 6th International Symposium on Applied Reconfigurable Computing (ARC), Bangkok, Thailand , 2010 [pdf] [link]

R. Chikhi, D. Lavenier, Paired-end read length lower bounds for genome re-sequensing, ISMB / ECCB, Stockholm, 2009 [link]

P. Perterlongo, J. Nicolas, D. Lavenier, R. Vorc h, J. Querellou, c-GAMMA: comparative genome analysis of molecular markers, 4th IAPR International Conference on Pattern Recognition in Bioinformatics, LNCS 5780 , Sheffield, UK, 2009 [pdf]

V.H. Nguyen, A. Cornu, D. Lavenier, Implementing protein seed-based comparison algorithm on the SGI RASC-100 platform, IPDPS, 16th Reconfigurable Architectures Workshop , Rome, Italy, 2009 [pdf]

G. Rizk, D. Lavenier, GPU accelerated Rna folding algorithm, International Conference on Computational Science, LNCS 5544, Baton Rouge, Louisiana, U.S.A., 2009 [pdf]

G. Rizk, D. Lavenier, GPU accelerated Rna-Rna interaction algorithm, EMB Conference 2008: Leading Applications and Technologies in bioinformatics, Martina Franka (Taranto), Italy, 2008 [link]

Y. Xiaochun, V-H. Nguyen, D. Lavenier, F. Dongruy, Efficient Parallelization of a Protein Sequence Comparison Algorithm on Manycore Architecture, Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies, Dunedin, New Zealand, 2008 [pdf]

D. Lavenier, J. Jacques, Parallelizing the ACGT OncoSimulator, 3rd International Advanced Research Workshop on In Silico Oncology: Advances and Challenges, Istanbul, Turkey, 2008 [pdf]

V-H. Nguyen, D. Lavenier, Speeding up Subset Seed Algorithm for Intensive Protein Sequence Comparison, 6th International Conference on research, innovation & vision for the future, Ho Chi Minh Ville, Vietnam, 2008 [pdf]

D. Lavenier, Ordered Index Seed Algorithm for Intensive DNA Sequence Comparison, HiComb 2008: IEEE International Workshop on High Performance Computational Biology, Miami, Florida, 2008 [pdf]

M. Giraud, G. Kucherov, D. Lavenier, L. Noé, P. Peterlongo, Utilization of Subset Seeds on a Reconfigurable Architecture, LAW 2007 (Lonfon Algorithm Workshop), King's London College, London, UK, 2007 [pdf]

P. Peterlongo, L. Noé, D. Lavenier, G. Georges, J. Jacques, G. Kucherov, M. Giraud, Protein similarity search with subset seeds on a dedicated reconfigurable hardware, Parallel Bio-Computing, Gdansk, Poland, 2007 [pdf]

D. Lavenier, X. Xinchun, G. Georges, Seed-based Genomic Sequence Comparison using a FPGA/FLASH Accelerator, International IEEE Conference on Field Programmable Technology (FPT), Bangkok, Thailand, 2006 [pdf]

M. Giraud, P. Veber, D. Lavenier, Path-Equivalent Removals of Epsilon-Transitions in a Genomic Weighted Finite Automaton, 11th International Conference on implementation and application of Automata, Taipei, Taiwan, 2006 [pdf]

D. Lavenier, Fine-Grained Parallelism for Genomic Computation (invited speaker), SIAM Conf. on Parallel Processing for Scientific Computing, San Francisco, CA, 2006 [pdf]

O. Glorieux, M. Ferré, A, Fouilloux, I. Dupays, D. Raux, D. Lavenier, Y. Malthièry, P. Raynier, Y. Tourmen , Optimisation of the NCBI-BLAST code for high throughput in silico comparative genomics in the DEISA project, JOBIM 2005, Lyon, 2005 [pdf]

N. Ventroux, D. Lavenier, A Low Complex Scheduling Algorithm for Multi-Processor System-on-Chip, PDCN 2005 Parallel and Distributed Computing and Networks, Innsbruck, Austria, 2005 [pdf]

M. Giraud, D. Lavenier, Linear Encoding Scheme for Weighted Finite Automata, CIAA 2004: Ninth International Conference on Implementation and Application of Automata, LNCS 3317, Queen s University, Kingston, Ontario, Canada, 2004 [link]

M. Giraud, D. Lavenier, Dealing with Size Limits in a Hardware Encoding of Weighted Finite Automata, WATA 2004: Weighted Automata: Theory and Applications, Dresden, Germany, 2004 [pdf]

R. Andonov, D. Lavenier, P. Veber, N. Yanev, Dynamic programming for LR-PCR segmention of bacterium genomes, HiComb 2004: Third IEEE International Workshop on High Performance Computational Biology, Santa Fe, New Mexico, USA, 2004 [pdf]

S. Guyétant, D. Lavenier, Evaluation of anchoring scheme for fast DNA Sequence Alignment, ECCB 2003: European Conference on Computational Biology, Paris, France, 2003 [pdf]

N. Ben Zacour, M. Gautier, R. Andonov, D. Lavenier, P. Veber, A. Sorokin, Y. Le Loir,, GENOFRAG: a software to design primers optimized for whole genome scaning by long-range PCR amplification. Application to the study of Staphylococcus aureus genome plasticity, ECCB 2003 European Conference on Computatopnal Biology, Paris, France, 2003 [pdf]

D. Lavenier, D. Guyétant, S. Derrien, S. Rubini,, A reconfigurable parallel disk system for filtering genomic banks, ERSA 03, Engineering of Reconfigurable Systems and Algorithms , Las Vegas, Nevada, USA, 2003 [pdf]

D. Lavenier, H. Leroy, M. Mac Wing, R. Andonov, M. Hurfin, P. Raipin-Parvedy, L. Mouchard, F. Guinand,, GénoGRID: an experimental grid for genomic applications, HealthGrid 2003, Lyon, France, 2003 [pdf]

L. Lagadec, D. Lavenier, E. Fabiani, B. Pottier,, Placing, Routing and Editing Virtual FPGAs, FPL 2001, 11th International Conference on Field Programmable Logic and Applications, Belfast, Northern Ireland, U.K., 2001 [pdf] [link]

Y. Solihin, K. Cameron, Y. Luo, D. Lavenier, M. Gokhale, Mutable Functional Units and their Applications on Microprocessors, ICCD 2001, International Conference on Computer Design, Austin, Texas, USA, 2001 [pdf]

D. lavenier, E. Fabiani, S. Derrien, C. Wagner, Systolic Array for computing the pixel purity index (PPI) algorithm on hyperspectral images, SPIE Conference on Imaging Spectrometry, San Diego, CA, USA, 2001 [pdf]

E. Fabiani, D. Lavenier, Experimental evaluation of place-and-route of regular arrays on Xilinx chips, International Conference on Engineering of Reconfigurable Systems and Algorithms, as Vegas, Nevada, USA, 2001 [pdf]

M. Gokhale, J. Frigo, K. McCabe, J. Theiler, D. Lavenier, Early Experience with a Hybrid Processor: K-Means Clustering, International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, 2001 [pdf]

Y. Solihin, K. Cameron, Y. Luo, D. Lavenier, M. Gokhale, Mutable Functional Units: Initial Results, IEEE Symposium on Field-Programmable Custom Computing Machines, ohnert Park, CA, USA, 2001

J. Frigo, M. Gokhale, D . Lavenier, Evaluation of the Streams-C C-to-FPGA Compiler: An Application Perspective, 9th ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 2001 [pdf]

D. Lavenier, J. Theiler, J. Szymanski, M. Gokhale, J. Frigo, FPGA Implementation of the Pixel Purity Index Algorithm , Boston, MA, USA, PIE Photonics East, Workshop on Reconfigurable Architectures, 2000 [pdf]

J. Szymanski, P. Blain, J. Bloch, C. Brislawn, S. Brumby, M. Caffrey, M. Dunham, J. Frigo, M. Gokhale, N. Harvey, G. Kenyon, W. Kim, J. Layne, D. Lavenier, K. McCabe, M. Mitchell, K. Moore, S. Perkins, R. Porter, S. Robinson, A. Salazar, J. Theiler, A. Young, Advanced processing for high-bandwith sensor systems, SPIE International Conference on Optical Science and Technology, San Diego, CA, USA, 2000 [pdf]

J. Theiler, D. Lavenier, N. Harvey, S. Perkins, J. Szymanski, Using blocks of skewers for faster computation of pixel purity index, SPIE International Conference on Optical Science and Technology, San Diego, CA, USA, 2000 [pdf]

E. Fabiani, D. Lavenier, Placement of Linear Arrays, FPL 2000, 10th International Conference on Field Programmable Logic and Applications, Villach, Austria, 2000 [pdf]

D. Lavenier, Y. Solihin, K. Cameron, Reconfigurable Arithmetic and Logic Unit, SympA 6, 6ème Symposium en Architecture de Machines, Besancon, FRANCE, 2000 [pdf]

J. Mosser, N. Soriano, F. Wojcik, V. Douabin, H. Ferran, S. Sachot, D. Lavenier, R. Moirand, Y. Deugnier, JY. Le Gall, V. David, A systematic approach for investigating primary iron overloads : Generation of iron-related SNPs, 49th Annual Meeting of the American Society of Human Genetics Applications, San Francisco, CA, USA, 1999

E. Fabiani, D. Lavenier, L. Perraudeau, Loop Parallelization on a Reconfigurable Coprocessor, Workshop on Design, Test and Applications, Subrovnik, Croatia, 1998 [pdf]

D. Lavenier, Y. Saouter, Computing Goldbach partitions using pseudo-random bit generator operators on a FPGA systolic array, 8th International Conference on Field Programmable Logic and Applications, Tallin, Estonia, 1998 [pdf]

D. Lavenier, JL. Pacherie, Parallel Processing for Scanning Genomic Data-Bases, ParCo 97, International Conference on Parallel Computing, Bonn, Germany, 1997 [pdf]

P. Guerdoux-Jamet, D. Lavenier, C. Wagner, P. Quinton, Design and Implementation of a Parallel Architecture for Biological Sequence Comparison, EuroPar 96, European Conference on Parallelism, Lyon, France, 1996 [pdf]

P. Guerdoux-Jamet, D. Lavenier, Systolic Filter for fast DNA Similarity Search, ASAP'95, International Conference on Application Specific Array Processors, Strasbourg, France, 1995 [pdf]

D. Lavenier, From Behavioral to RTL Model : an approach, 5th Internationnal Workshop on Rapid System Prototyping, Grenoble, France, 1995

JP. Banâtre, D. Lavenier, M. Viellot, From High Level Programming Model to FPGA Machines, 3rd Annual IEEE Symposium on FPGAs for Custom Computing Machine, Napa, CA, USA, 1994

D. Lavenier, An Integrated 2-D Systolic Array for String Comparison, First South American Workshop on String Processing, Belo Horizonte, Brazil, 1993

F. Raimbault, D. Lavenier, Relacs for Systolic Programming, ASAP'93, International Conference on Application Specific Array Processors, Venice, Italy, 1993

P.Frison, D. Lavenier, F. Raimbault, I/O Data Management on SIMD Systolic Arrays, ASAP'93, International Conference on Application Specific Array Processors, Venice, Italy, 1993

D. Lavenier, B. Pottier, F. Raimbault, S. Rubini, Fine grain parallelism on a MIMD machine using FPGAs, 1st IEEE Symposium on FPGAs for Custom Computing Machine, Napa, CA, USA, 1993

D. Lavenier, A High Performance Systolic Chip for Spelling Correction, Euro-Asic'92, Paris, France, 1992 [pdf]

P. Frison, D. Lavenier, Experience in the Design of Parallel Processor Arrays, Internationnal Workshop on Algorithms and Parallel VLSI Architectures II, Bonas, France, 1991

P. Frison, D. Lavenier, A Fully Integrated Systolic Spelling Co-processor, VLSI'91, Edinburgh, Scotland, 1991

P. Frison, E. Gautrin, D. Lavenier, J-L. Scharbarg, Designing Specific Systolic Array with the API15C chip, Application Specifique Array Processor, Princeton, NJ, USA, 1990

D. Lavenier, B. Pottier, High Rate Sigma Filtering, Feasibility Studies on Processors Networks, Workshop on Parallel Architectures on Silicon, Grenoble, France, 1989

P. Frison, D. Lavenier, H. Leverge, P. Quinton, A VLSI Programmable Systolic Architecture, International Conference on Systolic Array, Killarney, Irland , 1989

P. Frison, E. Gautrin, D. Lavenier, J-L. Scharbarg, API15C A Programmable Chip for Systolic Architecture, Workshop on Parallel Architectures on Silicon, Grenoble, France, 1989

P. Frison, D. Lavenier, A VLSI Systolic Machine for String Correction, Third International Conference on Supercomputing, Boston, MA, USA, 1988

P. Frison, D. Lavenier, A Fast Machine for Prototyping Correction Algorithms, RIAO 88 : User Oriented Contend-based text and Image Handling, Boston, MA, USA, 1988