REPORTS

V.H. Nguyen, D. Lavenier, Fine-grained parallelization of similarity search between protein sequences, INRIA report RR-6513, 2008 [link]

R. Andonov, N. Yanev, D. Lavenier, P. Veber, Combinatorial approaches for segmenting bacterium genomes, INRIA report RR-4853, 2003 [link]

F. Raimbault, D. Lavenier, ROOM: Reconfigurable Object-Oriented Machines for Specific Applications, INRIA report RR-4588, 2002 [link]

D. Lavenier, FPGA Implementation of the K-means Clustering Algorithm for Hyper-Spectral Images, Los Alamos National Laboratory report LA-UR 00-3079, 2000 [pdf]

Y. Solihin, K. Cameron, Y. Luo, D. Lavenier, M. Gokhale, Boosting the Speed-up of Future Processor Architectures by using Mutable Fuctional Units, Los Alamos National Laboratory report LA-UR 99-6768, 1999 [pdf]

E. Fabiani, D. Lavenier, Using knapsack technique to place linear arrays on FPGA, IRISA report PI-1335, 2000 [pdf]

D. Lavenier, FPGA Implementation of the Pixel Purity Index Algorithm for Hyper-Spectral Images, Los Alamos National Laboratory report LA-UR 00-2466, 2000 [pdf]

D. Lavenier, Y. Solihin, K. Cameron, Integer/Floating-point Reconfigurable ALU, Los Alamos National Laboratory report LA-UR 99-5535, 1999 [pdf]

Y. Solihin, K. Cameron, Y. Luo, D. Lavenier, M. Gokhale, Reservation Station Architecture of Mutable Functional Unit Usage in Superscalar Processors, Los Alamos National Laboratory report LA-UR 99-6234, 1999

D. Lavenier, SAMBA: Systolic Accelerator for Molecular Biological Applications, INRIA report RR-2845, 1996 [link]

JP. Banātre D. Lavenier, M. Vieillot, From high level programming model to FPGA machines, INRIA report RR-2240, 1994 [link]

D. Lavenier, R. McConnell, A Component Model for Synchronous VLSI System Design, INRIA report RR-2285, 1994 [link]

D. Lavenier, An integrated 2D systolic array for spelling correction, INRIA report RR-1987, 1993 [link]

D. Lavenier, F. Raimbault, P. Frison, I/O and computation overlap on SIMD systolic arrays, INRIA report RR-2096, 1993 [link]

F. Raimbault, D. Lavenier, S. Rubini, P. Pottier, Fine grain parallelism on a MIMD machine using FPGAs, INRIA report RR-1983, 1993 [link]

F. Raimbault, D. Lavenier, ReLaCS for systolic programming , INRIA report RR-1981, 1993 [link]