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Dominique Lavenier
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HOME RESEARCH PUBLICATIONS TEACHING SOFTWARE | ||||||||
| BioWIC | PLAST | GASSST | ReMIX | RDisk | GenoFrag | SAMBA |
The design effort was estimated to 11 person/months: 1 month for functional specification and simulation, one month for architectural specification and simulation, 2 months for architectural synthesis, 2 month for chip testing, 0.5 month for board design, 4 month for interface design, and 0.5 month for final integration AlgorithmThe algorithm implemented on SAMBA belongs to the dynamic programming class. The recurrence equation comes from the Smith and Waterman algorithm. However, it has been parametrized to cover a larger scope. A similarity matrix is calculated recursively using the following equation:
alpha, beta, delta, hi and vi are parameters for tuning the algorithm to local or global search, with or without gap penalty ParallelizationThe sequence comparison on a linear systolic array proceeds as follows: one sequence (the query sequence) is stored into the array (one character per processor) and the other sequence flows from the left to right through the array. During each systolic step, one elementary matrix computation is performed on each processor. The result is available on the rightmost processor when the last character of the flowing sequence is output.
Compared to a sequential machine the speed-up for computing one query sequence of size N against a database of M residues is given by: (N x M) / N + M - 1 = N (considering that M >> N) N = size of the query
sequence (number of processors) ArchitectureSAMBA comprised a workstation (with its local disk), a systolic array made out of 128 VLSI full custom processors and a FPGA-Memory interface which fills the gap between a complete hardwired array of processors and a programmable Von Neuman machine.
SAMBA is controlled by a few procedure calls inside a normal C-program, without forcing the user to have specific knowledge of the structure of the accelerator and how it works. A library of basic procedures has been developed to be rapidly understood by programmers; but these procedures stay close enough to the accelerator hardware to provide efficient speed-up. Bibliography
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Last modified: Thu Oct 01 21:26:49 2009 |